Method and apparatus for long code generation in synchronous, multi-chip rate systems

ABSTRACT

A method and apparatus for long code generation in synchronous, multi-chip rate systems, wherein a first code sequence having a first bit rate, and a second code sequence having the first bit rate, the second code sequence being a time delay of the first code sequence, are multiplexed together, producing a desired long code.

FIELD OF THE INVENTION

[0001] The present invention is related in general to cellularcommunication systems, and, more particularly, to an improved method andsystem for long code generation in synchronous, multi-chip rate systems.

BACKGROUND OF THE INVENTION

[0002] In synchronous code division multiple access (CDMA)telecommunication systems, a long code generator is initialized by useof the forward link synchronization channel. The long code generator isused to separate users. For example, in the IS-95 system, each user getsa different time shift of the same pseudo noise (PN) sequence, which isthe long code. When two synchronized systems are running at multiple andrelated chip rates, handoffs from one system to the other may becomplicated because the state of the long code generator of the newsystem is not known. For example, CDMA 2000 has a Spreading Rate 1, alsoknown as 1×, having a chip rate of 1.2288 Mcps, and a Spreading Rate 3,also known as 3×, having a chip rate of 3.6864 Mcps. If the same longcode generator is used in each system, the long code generator in the 3×system runs three times as fast as the long code generator in the 1×system. This causes a problem when handing off from a 3× system to a 1×system, and vice versa. Due to the synchronous nature of the twosystems, it is difficult to download the long code generator state ofthe new system to the user during handoff.

[0003] In the example discussed above, it is optimum to have a 3× longcode generator that is derived from the 1× long code generator. In thisway, once the mobile station is accessing either system, it knows thelong code generator state of the other system, and handoffs aresimplified. Therefore, a need exists for an improved method andapparatus for long code generation in a synchronous, multi-chip ratesystem.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The novel features believed characteristic of the invention areset forth in the appended claims. The invention itself, however, as wellas a preferred mode of use, further objects, and advantages thereof,will best be understood by reference to the following detaileddescription of an illustrative embodiment when read in conjunction withthe accompanying drawings, wherein:

[0005]FIG. 1 illustrates a block diagram of an exemplary apparatus inaccordance with the present invention illustrating the extension of a 1×chip rate to an Nx chip rate;

[0006]FIG. 2 illustrates a block diagram of an alternate embodiment ofan exemplary apparatus in accordance with the present inventionillustrating the extension of a 1× chip rate to an Nx chip rate;

[0007]FIG. 3 illustrates a block diagram of an exemplary apparatus inaccordance with the present invention illustrating an example of a longcode generator for spreading rate 3; and

[0008]FIG. 4 illustrates a logical flowchart of the method for long codegeneration according to the method and system of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0009] Referring now to the figures, wherein like referenced numeralsdesignate like components, FIG. 1 illustrates a block diagram of anexemplary apparatus 100 in accordance with the present inventionillustrating the extension of a 1× chip rate to an Nx chip rate. Inaccordance with FIG. 1, encoder 102 is concatenated to the output 104 ofcode generator 106. In the preferred embodiment, code generator 106includes a long code generator comprising a PN sequence generator.However, it will be appreciated by those skilled in the art that anysequence generator capable of generating a sequence of random bits maybe used without departing from the spirit and scope of the presentinvention. In the preferred embodiment, both the long code generator 106and the encoder 102 are operated at the same bit or chip rate, which inthe preferred embodiment is the 1× or reference chip rate (i.e. 1.2288Mcps). Encoder 102 encodes code generator output 104, and produces aplurality of component or code sequences 110-114, which are received bymultiplexor 108. Multiplexor 108 multiplexes code sequences 110-114 andproduces an output code sequence 116. As will be appreciated by thoseskilled in art, the architecture depicted in FIG. 1 provides theflexibility of extending the long code sequence from the 1× chip rate toany future higher multiple and related chip rate. Multiplexer 108 hasclock input 118 operating at Nx chip rate so that the output sequence116 has the desired chip rate.

[0010] Referring now to FIG. 2, a block diagram of an alternateembodiment of an exemplary apparatus 200 in accordance with the presentinvention illustrating an example of a long code generator for spreadingrate N is shown. An encoder 202 is concatenated with the output 204 ofthe long code generator 206, which preferably is running at the 1× chiprate. Encoder 202 encodes code generator output 204, and produces aplurality of component or code sequences 205, 215, 225, which arereceived by multiplexor 208. Preferably, first component sequence 205 issubstantially similar to code generator output 204, and is input tomultiplexor 208. However, those skilled in the art will appreciate thatfirst component sequence 205 may be a delayed version of code generatoroutput 204. Second component sequence 215 is a delayed version of codegenerator output 204, wherein code generator output 204 is delayed by apredetermined amount at delay block 210. Third component sequence 225 isalso a delayed version of code generator output 204, wherein codegenerator output 204 is delayed by a second predetermined amount atdelay block 212, wherein the first and second predetermined delays mayor may not be the same. As shown in FIG. 2, the long code for spreadingrate N comprises N multiplexed component sequences 205, 215, 225, etc.,each having a chip rate of 1×. Multiplexor 208 has clock input 218operating at the Nx chip rate so that the output sequence 216 has thedesired chip rate.

[0011] Referring now to FIG. 3, a block diagram of an exemplaryapparatus 300 in accordance with the present invention illustrating anexample of a long code generator for spreading rate 3 is shown. A codemask 305, which in the preferred embodiment is a long code mask, isinput to code generator 306. As described above, code generator 306 ispreferably a long code generator. Long code mask 305 is applied overlong code generator 306 to generate a specific mobile station's longcode sequence. A systematic rate ⅓ convulational encoder 302 isconcatenated with the output 304 of the long code generator 306, whichis running at the 1× chip rate. Encoder 302 encodes code generatoroutput 304, and produces a plurality of component or code sequences 305,315, 325, which are received by multiplexor 308. In cdma2000 or TIAIS-2000.2 Physical layer Standard for cdma2000 Spread Spectrum Systems,the long code for spreading rate 1 has a chip rate of 1× or 1.2288 Mcps.As shown in FIG. 3, the long code for spreading rate 3 comprises threemultiplexed component sequences 305, 315, 325, each having a chip rateof 1.2288 Mcps. The first component sequence 305 comprises the long codefor spreading rate 1. The second component sequence 315 comprises themodulo-2 addition of the long code for spreading rate 1 and the longcode for spreading rate 1 delayed by a predetermined amount, which inthe preferred embodiment is {fraction (1/1.2288)} microseconds. Thethird component sequence 325 comprises the modulo-2 addition of the longcode for spreading rate 1 and the long code for spreading rate 1 delayedby another predetermined amount, which in the preferred embodiment is{fraction (2/1.2288)} microseconds. However, other predetermined amountsmay be used and still fall within the scope of the present invention. Ifcode generator output 304 is a maximum length pseudo-noise sequence, thesecond and third component sequences 315, 325 are delayed ortime-shifted versions of the first component sequence 305. As will beappreciated by those skilled in the art, the delay may be produced via ashift register, a multiplier, etc. However, it should be noted that thelength of the shift register may be prohibitive. The three componentsequences 305, 315, and 325 are multiplexed by multiplexer 308.Multiplexor 308 multiplexes code sequences 305, 315, 325 and produces anoutput code sequence 316. In this example, multiplexer 308 runs at achip rate three times that of spreading rate 1 (i.e. spreading rate 3)via clock input 318. Therefore, the long code for spreading rate 3 willhave a chip rate of 3.6864 Mcps. In the preferred embodiment, the threecomponent sequences 305, 315, and 325 are multiplexed such that the longcode value at the beginning of every {fraction (1/1.2288)} microsecondinterval, starting from the beginning of the System Time, corresponds tothe first component sequence.

[0012] As will be appreciated by those skilled in the art, the proceduredescribed above for spreading rate 3 can be extended to generate a longcode sequence of any multiple length. For example, a 4× long codesequence may be generated by multiplexing four 1× sequences: the threesequences above and a fourth sequence generated by delaying the longcode for spreading rate 1 by yet another predetermined amount, which inthe preferred embodiment is three chips or {fraction (3/1.2288)}microseconds, and exclusive or'ing or performing a modulo-2 additionwith spreading rate 1.

[0013] With reference now to FIG. 4, there is depicted a logicalflowchart of the process 400 of long code generation according to themethod and system of the present invention. As shown, the process beginsat block 402, wherein the step of synchronizing to the system long codeis performed. Thereafter, as shown at block 404, the step of performingthe modulo-2 addition of the long code sequence for the 1× system andthe long code sequence for the 1× system delayed by a predeterminedamount is performed. Thereafter, as shown at block 406, the step ofperforming the modulo-2 addition of the long code sequence for the 1×system and the long code sequence for the 1× system delayed by anotherpredetermined amount is performed. Thereafter, as shown at block 408,the step of multiplexing together the three long code sequences isperformed, producing the 3× long code sequence.

[0014] The foregoing description of a preferred embodiment of theinvention has been presented for the purpose of illustration anddescription. It is not intended to be exhaustive or to limit theinvention to the precise form disclosed. Obvious modifications orvariations are possible in light of the above teachings. The embodimentwas chosen and described to provide the best illustration of theprinciples of the invention and its practical application, and to enableone of ordinary skill in the art to utilize the invention in variousembodiments and with various modifications as are suited to theparticular use contemplated. All such modifications and variations arewithin the scope of the invention as determined by the appended claimswhen interpreted in accordance with the breadth to which they arefairly, legally, and equitably entitled.

What is claimed is:
 1. A method for code generation in synchronous,multi-chip rate communication systems, comprising the steps of:producing a first code sequence having a first bit rate; producing asecond code sequence having the first bit rate, the second code sequencebeing a time delay of the first code sequence; and multiplexing thefirst code sequence and the second code sequence and producing an outputcode sequence having a desired bit rate.
 2. A method for code generationas recited in claim 1, wherein the step of producing the second codesequence comprises the step of performing modulo-2 addition of the firstcode sequence and a delayed version of the first code sequence.
 3. Amethod for code generation as recited in claim 1, including the step ofproducing a third code sequence having the first bit rate, the thirdcode sequence being a time delay of the first code sequence, wherein thestep of multiplexing includes multiplexing the third code sequence.
 4. Amethod for code generation as recited in claim 3, wherein the step ofproducing the second code sequence comprises the step of performingmodulo-2 addition of the first code sequence and a delayed version ofthe first code sequence, and wherein the step of producing the thirdcode sequence comprises the step of performing modulo-2 addition of thefirst code sequence and a second delayed version of the first codesequence.
 5. A method for long code generation in synchronous,multi-chip rate communication systems, comprising the steps of:producing a first long code sequence having a first bit rate; producinga second long code sequence having the first bit rate, the second longcode sequence being a time delay of the first code sequence; producing athird long code sequence having the first bit rate, the third long codesequence being a time delay of the first long code sequence; andmultiplexing the first long code sequence, the second long codesequence, and the third long code sequence, and producing an output codesequence having a desired bit rate.
 6. A method for long code generationas recited in claim 5, wherein the step of producing the second longcode sequence comprises the step of performing modulo-2 addition of thefirst code sequence and a delayed version of the first code sequence,and wherein the step of producing the third code sequence comprises thestep of performing modulo-2 addition of the first code sequence and asecond delayed version of the first code sequence.
 7. An apparatus forcode generation in synchronous, multichip rate systems, comprising: acode generator adapted to produce a first code sequence having a firstbit rate; an encoder coupled to the code generator and adapted toreceive the first code sequence, the encoder adapted to produce a secondcode sequence having the first bit rate, and a multiplexor coupled tothe encoder, the multiplexer adapted to receive the first code sequenceand the second code sequence, the multiplexor further adapted to producean output code sequence having a desired bit rate.
 8. An apparatus forcode generation as recited in claim 7, wherein the encoder comprises adelay block coupled to the first code sequence, the delay block adaptedto produce a delayed first code sequence having a predetermined delaytime; and a modulo-2 addition block coupled to the delay block and tothe multiplexor, the modulo-2 addition block adapted to perform modulo-2addition of the first code sequence and the time delayed first codesequence.
 9. An apparatus for code generation as recited in claim 7,wherein the encoder is further adapted to produce a third code sequencehaving the first bit rate, the third code sequence being a time delay ofthe first code sequence, wherein the multiplexor is adapted to receivethe third code sequence.
 10. An apparatus for code generation as recitedin claim 8, wherein the encoder comprises a second delay block coupledto the first code sequence, the second delay block adapted to produce asecond delayed first code sequence having a second predetermined delaytime; and a second modulo-2 addition block coupled to the second delayblock and to the multiplexor, the second modulo-2 addition block adaptedto perform modulo-2 addition of the first code sequence and the seconddelayed first code sequence.
 11. An apparatus for long code generationin synchronous, multi-chip rate communication systems, comprising: along code generator adapted to produce a first long code sequence havinga first bit rate; a convolutional encoder coupled to the long codegenerator and adapted to receive the first long code sequence, theconvolutional encoder adapted to produce a second long code sequencehaving the first bit rate, the convolutional encoder further adapted toproduce a third long code sequence having the first bit rate; and amultiplexor coupled to the convolutional encoder, the multiplexoradapted to receive the first long code sequence, the second long codesequence, and the third long code sequence, the multiplexor furtheradapted to produce an output long code sequence having a desired bitrate.
 12. An apparatus for long code generation as recited in claim 11,wherein the convolutional encoder comprises a first delay block coupledto the first code sequence, the first delay block adapted to produce adelayed first code sequence having a predetermined delay time; and afirst modulo-2 addition block coupled to the first delay block, thefirst modulo-2 addition block adapted to perform modulo-2 addition ofthe first code sequence and the delayed first code sequence.
 13. Anapparatus for long code generation as recited in claim 12, wherein theconvolutional encoder further comprises a second delay block coupled tothe first code sequence, the second delay block adapted to produce asecond delayed first code sequence having a second predetermined delaytime; and a second modulo-2 addition block coupled to the second delayblock and to the multiplexor, the second modulo-2 addition block adaptedto perform modulo-2 addition of the first code sequence and the seconddelayed first code sequence;